1. Field of the Invention
The present invention relates to a ferroelectric random access memory (FERAM) cell, and in particular to a method of fabricating a ferroelectric (FE) capacitor on a complementary metal oxide semiconductor (CMOS) structure wherein exposure of the integrated structure to high temperature steps of FE deposition and processing is eliminated. The present invention also relates to a FERAM cell design and to a method to bond a FE capacitor to the CMOS structure after fabrication of both structures is complete, thereby avoiding the incompatibilities between the two processes. The resulting structure can be used as a non-volatile RAM (NVRAM) or a dynamic random access memory (DRAM), if the FE material is replaced with a material of high-dielectric-constant.
2. Background of the Invention
The integration of high value capacitors in integrated circuits (ICs) is limited by the fact that conventional high value capacitors take up large areas of the IC chip, thus reducing device packing density and layout efficiency. Many applications require a large number of capacitors. Often the capacitors must be incorporated as discrete off-chip components, substantially increasing the bulk of the peripheral circuitry. In view of the increasing demand for compact lightweight electronic equipment, it is desirable that the number of discrete components be reduced.
The minimum dimensions of IC capacitors are determined primarily by the relatively low dielectric constant (0 less than 10) of conventional capacitor dielectrics, e.g. SiO2 and Si3N4. Thus, as device dimensions decrease, there is increasing interest in other dielectrics having higher dielectric constants than conventional dielectric materials.
Ferroelectric (FE) and high-epsilon (HE) dielectrics (0=20 or greater) have found application in random access memory (RAM) cells since they provide for the formation of NVRAMs and DRAMs. Moreover, when used as NVRAM, ferroelectric dielectrics advantageously provide low voltage programmability, fast access times and low power consumption.
FE materials pose several integration problems. In particular, most ferroelectric materials require high temperature post-deposition oxygen anneals (600xc2x0 C. or above) to achieve properties desirable for storage media. However, such high anneal temperatures can be incompatible with the CMOS devices already fabricated on the wafer. Furthermore, any subsequent forming gas or hydrogen anneals (highly desirable for CMOS devices) degrade the ferroelectric material, thus requiring additional high temperature oxygen anneals late in the processing sequence which in turn are detrimental to the CMOS circuitry. In view of the above drawbacks with prior art methods of integrating ferroelectric capacitors with CMOS structures, there is a continued need for developing a new and improved method which is capable of providing an integrated FE capacitor/CMOS structure without subjecting the CMOS structure to high temperature steps that are typically required in the prior art for ferroelectric processing.
The present invention provides a method of integrating a FE capacitor with a CMOS structure which allows the CMOS structure to avoid potentially-detrimental high-temperature steps needed for FE deposition and processing. The invention likewise provides a method of integrating a plurality of FE capacitors with a plurality of CMOS structures. Specifically, the method of the present invention comprises the steps of:
(a) forming a CMOS structure in electrical contact with a conductive electrode layer on its exposed top surface;
(b) separately providing a ferroelectric delivery wafer, said ferroelectric delivery wafer comprising a sacrificial release layer formed on a delivery substrate, a conductive layer formed on said sacrificial release layer and a ferroelectric film formed on said conductive layer, said ferroelectric film having an exposed outer surface;
(c) placing said exposed outer surface of said ferroelectric film on the CMOS structure of step (a), wherein said ferroelectric film is in contact with said conductive electrode layer;
(d) bonding, at a temperature of less then about 600xc2x0 C., the outer surface of said ferroelectric electrode layer;
(e) separating the sacrificial release layer from the bonded structure.
It is noted that the conductive electrode layer of the CMOS structure of step (a) may be patterned or unpatterned. Likewise, the conductive layer of the delivery wafer may also be patterned or unpatterned.
If not previously patterned, one or more of the conductive layers in the integrated FE capacitor/CMOS structure may optionally be patterned. This optional patterning step occurs after step (e) above.
Another embodiment of the present method is to apply a surface treatment to the conductive electrode layer of the CMOS structure prior to conducting step (c). In yet another embodiment of the present invention, the method also includes a step of forming a passivating layer over the structure provided in step (e). In still a further embodiment of the present invention, the delivery wafer may include a second conductive layer on top of the ferroelectric film. In this embodiment of the invention, the second conductive layer may be patterned or unpatterned. In another aspect of the present invention, a novel integrated FE/CMOS structure is provided wherein the storage capacitor is constructed over all the transistors and wiring levels (excluding possibly any pad out structures) of the CMOS structure. Specifically, the novel integrated FE/CMOS structure of the present invention comprises:
a CMOS structure having at least one conductive layer and at least one transistor; and
a ferroelectric storage capacitor formed on said CMOS structure, said ferroelectric storage capacitor comprising a bottom conductive electrode, a layer of ferroelectric film and a top conductive electrode, wherein said bottom conductive electrode of said capacitor is connected to a terminal of said transistor through one or more conductive layers of said CMOS structure.
The present invention also provides a novel ferroelectric delivery wafer which allows for fabricating an integrated FERAM cell while isolating the CMOS circuitry from high temperature post-FE-deposition anneals. That is, although high temperature anneals are used in forming the separate CMOS and ferroelectric structures, and bonding thereof, no such anneals are needed thereafter. Specifically, the ferroelectric delivery wafer of the present invention comprises a carrier substrate, a sacrificial release layer formed on said carrier substrate, a conductive layer formed on said sacrificial release layer, and a ferroelectric film formed on said conductive layer. This structure is flipped onto a CMOS structure so that the ferroelectric film is in contact with a CMOS structure having an upper conductive electrode layer. After conducting steps (a) and (e) above, an integrated FE/CMOS structure in accordance with the present invention, is formed.